There are a number of challenges that scaling of conventional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) are faced with. For example, threshold swing degradation, large drain-induced barrier lowering (DIBL), device characteristics fluctuations, and leakage are among the most common problems that may be addressed by 3-D device structures. Fin field-effect transistors (FinFETs) are 3-D device structures that can be used in nano-scale complementary metal-oxide-semiconductor (CMOS) and high-density memory applications. FinFETs with lateral double-diffused MOS (LDMOS) structures, which are mostly used in RF power amplifiers, can provide a high breakdown voltage between drain and source terminals). The high breakdown voltage is achieved, for example, by a charge carrier (e.g., electron) flow path that passes through a depletion region.